Re: [PATCH v0 04/71] itrace: Infrastructure for instruction flow tracing units

[Alexander Shishkin]

Peter Zijlstra <peterz@xxxxxxxxxxxxx> writes:

> On Wed, Dec 18, 2013 at 04:22:36PM +0200, Alexander Shishkin wrote:
>> > Still confused, if you cannot copy it into one buffer, then why can you
>> > copy it into a second buffer?
>> 
>> It's not copied, hardware writes directly into that second buffer.
>
> Where's the PT documentation? I can't find it in the SDM and your ISA
> extensions link is a generic Intel website which is friggin useless
> (like all corporate websites strive to be).

[1]

> Your actual PT patch doesn't describe how the things works either, and
> while I could go read the code, I'm too lazy.
>
> The thing is; why can't you zero-copy whatever buffer the hardware
> writes into, into the normal buffer?

I'm not sure I understand. You mean, have the buffer split between perf
data and trace data?

> Machinery like that would also be useful to zero-copy bits out of the
> buffer right into the page-cache.

Please elaborate.

>> I've done the same with BTS now (as Ingo suggested) and it also benefits
>> from this approach.
>
> The problem with DS is that it needs physically contiguous pages is it
> not? So you cannot really allocate a large buffer, and you end up
> needing to copy or swizzle stuff.

Yes and some implementations of PT have the same issue, but you can do a
sufficiently large high order allocation and map it to userspace and
still no copying (or parsing/decoding) in kernel space required.

[1] http://download-software.intel.com/sites/default/files/managed/71/2e/319433-017.pdf

Regards,
--
Alex
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