Re: [PATCH] x86: Add check for number of available vectors before CPUdown [v2]

From: rui wang
Date: Mon Dec 30 2013 - 07:56:18 EST

On 12/29/13, Prarit Bhargava <prarit@xxxxxxxxxx> wrote:
> On 12/20/2013 04:41 AM, rui wang wrote:
>> The vector number for an irq is programmed in the LSB of the IOAPIC
>> IRTE (or MSI data register in the case of MSI/MSIx). So there can be
>> only one vector number (although multiple CPUs can be specified
>> through DM). An MSI-capable device can dynamically change the lower
>> few bits in the LSB to signal multiple interrupts with a contiguous
>> range of vectors in powers of 2,but each of these vectors is treated
>> as a separate IRQ. i.e. each of them has a separate irq desc, or a
>> separate line in the /proc/interrupt file. This patch shows the MSI
>> irq allocation in detail:
>> Thanks
>> Rui
> Gong and Rui,
> After looking at this in detail I realized I made a mistake in my patch by
> including the check for the smp_affinity. Simply put, it shouldn't be
> there
> given Rui's explanation above.
> So I think the patch simply needs to do:
> this_count = 0;
> for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++)
> {
> irq = __this_cpu_read(vector_irq[vector]);
> if (irq >= 0) {
> desc = irq_to_desc(irq);
> data = irq_desc_get_irq_data(desc);
> affinity = data->affinity;
> if (irq_has_action(irq) && !irqd_is_per_cpu(data))
> this_count++;
> }
> }
> Can the two of you confirm the above is correct? It would be greatly
> appreciated.

An irq can be mapped to only one vector number, but can have multiple
destination CPUs. i.e. the same irq/vector can appear on multiple
CPUs' vector_irq[]. So checking data->affinity is necessary I think.
But notice that data->affinity is updated in chip->irq_set_affinity()
inside fixup_irqs(), while cpu_online_mask is updated in
remove_cpu_from_maps() inside cpu_disable_common(). They are updated
in different places. So the algorithm to check them against each other
should be different, depending on where you put the check_vectors().
That's my understanding.

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