[PATCH] x86/apic: Reinstate error IRQ Pentium erratum 3AP workaround
From: Maciej W. Rozycki
Date: Tue Apr 01 2014 - 08:30:38 EST
A change introduced with commit 60283df7ac26a4fe2d56631ca2946e04725e7eaf
[x86/apic: Read Error Status Register correctly] removed a read from the
APIC ESR register made before writing to same required to retrieve the
correct error status on Pentium systems affected by the 3AP erratum:
"3AP. Writes to Error Register Clears Register
PROBLEM: The APIC Error register is intended to only be read. If there is
a write to this register the data in the APIC Error register will be
cleared and lost.
IMPLICATION: There is a possibility of clearing the Error register status
since the write to the register is not specifically blocked.
WORKAROUND: Writes should not occur to the Pentium processor APIC Error
STATUS: For the steppings affected see the Summary Table of Changes at the
beginning of this section."
The steppings affected are actually: B1, B3 and B5.
To avoid this information loss this change avoids the write to ESR on all
Pentium systems where it is actually never needed; in Pentium processor
documentation ESR was noted read-only and the write only required for
future architectural compatibility. The approach taken in the same as
 "Pentium Processor Family Developer's Manual", Intel Corporation,
1997, order number 241428-005, Appendix A "Errata and S-Specs for the
Pentium Processor Family", p. A-92,
 "Pentium Processor Family Developer's Manual, Volume 3: Architecture
and Programming Manual", Intel Corporation, 1995, order number
241430-004, Section 19.3.3. "Error Handling In APIC", p. 19-33.
Signed-off-by: Maciej W. Rozycki <macro@xxxxxxxxxxxxxx>
@@ -1989,7 +1989,8 @@ static inline void __smp_error_interrupt
/* First tickle the hardware, only then report what went on. -- REW */
- apic_write(APIC_ESR, 0);
+ if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
+ apic_write(APIC_ESR, 0);
v = apic_read(APIC_ESR);
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