Re: [PATCH 00/18] Cross-architecture definitions of relaxed MMIO accessors

[Will Deacon]

Hi Peter,

On Thu, Apr 17, 2014 at 03:00:36PM +0100, Peter Zijlstra wrote:
> On Thu, Apr 17, 2014 at 02:44:03PM +0100, Will Deacon wrote:
> > In actual fact, the relaxed accessors *are* ordered with respect to LOCK/UNLOCK
> > operations on ARM[64], but I have added this constraint for the benefit of
> > PowerPC, which has expensive I/O barriers in the spin_unlock path for the
> > non-relaxed accessors.
> > 
> > A corollary to this is that mmiowb() probably needs rethinking. As it currently
> > stands, an mmiowb() is required to order MMIO writes to a device from multiple
> > CPUs, even if that device is protected by a lock. However, this isn't often used
> > in practice, leading to PowerPC implementing both mmiowb() *and* synchronising
> > I/O in spin_unlock.
> > 
> > I would propose making the non-relaxed I/O accessors ordered with respect to
> > LOCK/UNLOCK, leaving mmiowb() to be used with the relaxed accessors, if
> > required, but would welcome thoughts/suggestions on this topic.
> 
> So the non-relaxed ops already imply the expensive I/O barrier (mmiowb?)
> and therefore, PPC can drop it from spin_unlock()?

Ben can probably help out here, but if my proposal went ahead (that is,
only the non-relaxed ops would imply mmiowb()), then it would actually
be implemented on PPC by having only those accessors call IO_SET_SYNC_FLAG,
which is checked during unlock (in SYNC_IO).

> Also, I read mmiowb() as MMIO-write-barrier(), what do we have to
> order/contain mmio-reads?

My understanding is that this is related to posted stores from different
CPUs being re-ordered on the bus, so I wouldn't expect reads to suffer
(although, since this isn't permitted on ARM, I'm guessing here).

Will
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