Re: [PATCH v2 13/18] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance

From: Tero Kristo
Date: Thu Jun 19 2014 - 07:21:14 EST


On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.

Drop the ref to the binding doc and rather add a ref to TRM about the clock layout. Also, is the register offset wrong on these? Should be 0x13b8, no, or is my TRM version wrong?

-Tero


Cc: Rajendra Nayak <rnayak@xxxxxx>
Cc: Tero Kristo <t-kristo@xxxxxx>
Cc: Paul Walmsley <paul@xxxxxxxxx>
Cc: Tony Lindgren <tony@xxxxxxxxxxx>
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Pawel Moll <pawel.moll@xxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Cc: Kumar Gala <galak@xxxxxxxxxxxxxx>
Signed-off-by: Keerthy <j-keerthy@xxxxxx>
Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 3d8c9c2..a9ff0dc 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1173,6 +1173,14 @@
ti,bit-shift = <8>;
};

+ optfclk_pciephy2_32khz: optfclk_pciephy_32khz@4a0093b4 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b4>;
+ ti,bit-shift = <8>;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
@@ -1191,6 +1199,14 @@
ti,bit-shift = <9>;
};

+ optfclk_pciephy2_clk: optfclk_pciephy_clk@4a0093b4 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b4>;
+ ti,bit-shift = <9>;
+ };
+
optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
@@ -1199,6 +1215,14 @@
ti,bit-shift = <10>;
};

+ optfclk_pciephy2_div_clk: optfclk_pciephy_div_clk@4a0093b4 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x13b4>;
+ ti,bit-shift = <10>;
+ };
+
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/