Re: [PATCH V2 1/3] perf ignore LBR and offcore_rsp.

From: Andi Kleen
Date: Wed Jul 02 2014 - 22:16:59 EST


> Signed-off-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>

I did not contribute to this patch, so please remove that SOB.

> Signed-off-by: Kan Liang <kan.liang@xxxxxxxxx>

> struct extra_reg *extra_regs;
> unsigned int er_flags;
> + bool extra_msr_access; /* EXTRA REG MSR can be accessed */
>

This doesn't look right, needs a flag for each extra register.

They are completely unrelated to each other.

BTW this will also cause KVM messages at each boot now.

> wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
> wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
> }
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index adb02aa..8011d42 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2565,6 +2565,13 @@ __init int intel_pmu_init(void)
> }
> }
>
> + /* Access LBR MSR may cause #GP under certain circumstances. E.g. KVM doesn't support LBR MSR */
> + if (x86_pmu.lbr_nr)
> + x86_pmu.lbr_msr_access = test_msr_access(x86_pmu.lbr_tos) & test_msr_access(x86_pmu.lbr_from);

s/&/&&/

And also this doesn't cover the case when someone takes over the LBRs and they start #GPing later.
So for LBR the test has to be still at each access.

-Andi
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