Re: [PATCH RFC v4 net-next 01/26] net: filter: add "load 64-bit immediate" eBPF instruction

From: Alexei Starovoitov
Date: Wed Aug 13 2014 - 17:02:58 EST

On Wed, Aug 13, 2014 at 11:35 AM, Andy Lutomirski <luto@xxxxxxxxxxxxxx> wrote:
> The compiler can still think of it as a single insn, though, but some
> future compiler might not.

I think that would be very dangerous.
compiler (user space) and kernel interpreter must have the same
understanding of ISA.

> In any case, I think that, if you use the
> same code for high and for low, you need logic in the JIT that's at
> least as complicated.

why do you think so? Handling of pseudo BPF_LD_IMM64 is done
in single patch #11 which is one of the smallest...

> For example, what happens if you have two
> consecutive 64-bit immediate loads to the same register? Now you have
> four consecutive 8-byte insn words that differ only in their immediate
> values, and you need to split them correctly.

I don't need to do anything special in this case.
Two 16-byte instructions back to back is not a problem.
Interpreter or JIT don't care whether they move the same or different
immediates into the same or different register. Interpreter and JITs
are dumb on purpose.
when verifier sees two back to back ld_imm64, the 2nd will simply
override the value loaded by first one. It's not any different than
two back to back 'mov dst_reg, imm32' instructions.
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