Re: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325
From: Will Deacon
Date: Tue Aug 26 2014 - 06:14:02 EST
On Mon, Aug 18, 2014 at 10:58:09AM +0100, Kever Yang wrote:
> From: Huang Tao <huangtao@xxxxxxxxxxxxxx>
> On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of
> two conditional store instructions with opposite condition code and
> updating the same register, the system might enter a deadlock if the
> second conditional instruction is an UNPREDICTABLE STR or STM
> instruction. This workaround setting bit of the Feature Register
> prevents the erratum. This bit disables an optimisation applied to a
> sequence of 2 instructions that use opposing condition codes.
> Signed-off-by: Huang Tao <huangtao@xxxxxxxxxxxxxx>
> Signed-off-by: Kever Yang <kever.yang@xxxxxxxxxxxxxx>
The Rk3288 I have advertises itself as an r0p1 Cortex-A12 CPU, so isn't
affected by this issue. Until we have an SoC supported in mainline that
requires this workaround, I don't think we should merge it.
Also, please consider setting these bits in your firmware if possible.
The feature register isn't writable from the non-secure side, so if you
want to use virtualisation you'll need to do this differently.
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/