Re: [PATCH] x86: Intel Cache Allocation Technology support

From: Vikas Shivappa
Date: Fri Nov 21 2014 - 16:15:24 EST

On Fri, 21 Nov 2014, Borislav Petkov wrote:

On Fri, Nov 21, 2014 at 12:00:27PM -0800, Vikas Shivappa wrote:
+char hsw_brandstrs[5][64] = {
+ "Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz",
+ "Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz",
+ "Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz",
+ "Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz",
+ "Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz"
+#define cacheqe_for_each_child(child_cq, pos_css, parent_cq) \
+ css_for_each_child((pos_css), \
+ &(parent_cq)->css)

We really do NOT need another config option for this. See above.

+/*DUMP the closid-cbm map.*/

Wow that comment is really informative.

+static inline bool cqe_enabled(struct cpuinfo_x86 *c)
+ int i;
+ if (cpu_has(c, X86_FEATURE_CQE_L3))
+ return true;
+ /*
+ * Hard code the checks and values for HSW SKUs.
+ * Unfortunately! have to check against only these brand name strings.
+ */

You must be kidding.

No. Will have a microcode version check as well in next patch after thats
confirmed from h/w team

Checking random brand strings? Please don't tell me those are not really
immutable either...

And what happens with newer models appearing? Add more brand strings?
Lovely stuff, that.

Well, since you're talking to the h/w team: can they give you some
immutable bit somewhere which you can check instead of looking at brand
strings? This'll be a sane solution, actually.

Yes , I did check for something like model stepping , not received anything yet. will update in my next version.



Sent from a fat crate under my desk. Formatting is fine.

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