Re: [PATCH v15 12/12] drm: bridge/dw_hdmi: add rockchip rk3288 support

From: Andy Yan
Date: Wed Dec 03 2014 - 07:32:34 EST

Hi Philipp:
On 2014å12æ02æ 21:00, Philipp Zabel wrote:
Hi Andy,

Am Dienstag, den 02.12.2014, 20:34 +0800 schrieb Andy Yan:
Hi Philipp:
On 2014å12æ02æ 18:24, Philipp Zabel wrote:
Hi Andy,

Am Dienstag, den 02.12.2014, 15:45 +0800 schrieb Andy Yan:
+static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ void *data)
+ struct platform_device *pdev = to_platform_device(dev);
+ const struct dw_hdmi_plat_data *plat_data;
+ const struct of_device_id *match;
+ struct drm_device *drm = data;
+ struct drm_encoder *encoder;
+ struct rockchip_hdmi *hdmi;
+ int ret;
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+ hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
+ if (!hdmi)
+ return -ENOMEM;
+ match = of_match_node(dw_hdmi_rockchip_ids, pdev->dev.of_node);
+ plat_data = match->data;
+ hdmi->dev = &pdev->dev;
+ encoder = &hdmi->encoder;
+ platform_set_drvdata(pdev, hdmi);
+ ret = rockchip_hdmi_parse_dt(hdmi);
+ if (ret) {
+ dev_err(hdmi->dev, "Unable to parse OF data\n");
+ return ret;
+ }
+ ret = clk_prepare_enable(hdmi->clk);
+ if (ret) {
+ dev_err(hdmi->dev, "Cannot enable HDMI clock: %d\n", ret);
+ return ret;
+ }
+ ret = clk_prepare_enable(hdmi->hdcp_clk);
+ if (ret) {
+ dev_err(hdmi->dev, "Cannot enable HDMI hdcp clock: %d\n", ret);
+ return ret;
+ }
Could we have a look at the clocks again? Basically the Rockchip clock
handling is exactly the same, except the clocks are called by other

On i.MX6, according to the reference manual, the HDMI TX module has four
clock inputs: "iahbclk" (bus clock), "icecclk" (32 kHz CEC clock),
"ihclk" (module clock), and "isfrclk" (27 MHz internal SFR clock).
The "iahbclk" and "ihclk" are both sourced from the SoC AHB root clock,
the 32 kHz reference input can't be gated, and the "isfrclk" has its own

Does the HDMI TX implementation on Rockchip still have the separate
external sfr bus and module clock inputs? I assume that your "clk" input
is a single gate bit for bus and module clocks at the same time?
If possible, I'd prefer to find a common binding for the clocks with
some of the clocks being optional, but for that we need to know the
actual clock inputs to the HDMI TX module.


There are three individual clock inputs on Rockchip RK3288 HDMI:
"hdmi_cec_clk", "hdmi_hdcp_clk", the three clocks are responsible
for different
functions as their name described, and have their own private gate
bit. That is
to say, the cec_clk and hdcp_clk can all be disabled if we don't
need hdcp and cec
So I think it's better to make the clk control platform independent.
My question is not about the available gates at the SoC level, but about
the actual clock inputs from point of view of the HDMI TX IP.

It could be that the hdmi_ctrl_clk gates all inputs to the module and
bus clocks together. If so, you could just reuse "isfr" and "iahb" and
set it to the same clock. If not, we'd need to think of something else.
Unfortunately I don't have any Synopsys documentation of the HDMI TX at
that level.

After confirming with the IC designer, we finally make clear that
Rockchip RK3288 almost use the same clock design with imx:
clk-----iahbclk, used for hdmi module and bus
hdcp_clk-----isfrclk, used for hdcp and i2cm
cecclk -----cecclk, but this clk can be gated on rockchip, this is different with imx,
but we don't handle the cec stuff now. So i will try to reuse the imx clk binds. do you
think that is ok?

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