Re: Question about patch "i2c: omap: resize fifos before each message"

From: Felipe Balbi
Date: Wed Dec 03 2014 - 14:38:35 EST


On Wed, Dec 03, 2014 at 10:01:33PM +0300, Alexander Kochetkov wrote:
> 03 ÐÐÐ. 2014 Ð., Ð 20:49, Felipe Balbi <balbi@xxxxxx> ÐÐÐÐÑÐÐ(Ð):
> > It can also be a master receiver and a
> > slave transmitter.
> Agree, but this unrelated to races.
> > Note also that MST bit does *not* auto clear.
> Yes, it *does* auto clear!
> MST bit automatically clear when IP receive AL.
> See TRM [1]. All other TRMs (omap3530, omap3430,
> omap4, omap5) has the same picture.
> From TRM:
> 2Ci.I2C_CON[10] MST bits are cleared by hardware
> And MST bit clear after IP send STP (success transfer).
> Did you see what value is in CON register after successful master
> transfer? Apply my patch and see that.
> It doesn't have MST bit set. That mean IP is in slave mode (receiver
> or transmitter - doesn't matter) after *any* master transfer.
> And simple test show that. IP respond to GC address (address 0).
> And respond to SA address (if programmed).
> And TRM[1] figure has comment for 'end' state:
> "I2C controller goes into slave receiver mode."

had completely missed that comment. Right, IP will switch over into
slave mode. Still, as of today, this can't happen because Multimaster
isn't supported :-)

> And IP keeps into slave mode until 'suspend'.
> Then, after 'resume' IP initialized into slave receiver mode. There is
> short time after resume and master start initialize new transfer.
> So, then we start new transfer IP could start receiving slave command.

you'd first receive an interrupt which would let you figure out if the
interrupt was for Slave or Master modes. Then you can do anything you
want (set a flag that you're going into slave mode and return -EAGAIN on
any master transfer request for example).

> > Also,
> > the IP won't do anything (considering it's always in master mode) until
> > STT bit is set again
> Yes, it do slave reception or tranmittion with STT bit set to 0.
> You could set STT bit to 1, and then it got cleared to 0, you
> now, that IP received Start condition with slave transfer.
> You could leave STT bit set to 0, but IP still respond to slave transfer.
> (at least the IP on dm3730).
> And we can't set MST bit again after master transfer to leave IP in the
> master mode. We must disable IP (clear EN bit) before transfers to
> disable slave mode, or we must handle slave interrupts.

then handle slave interrupts :-) But handle them so that it won't race
with a master transfer request. Moving omap_i2c_xfer() inside the IRQ
handler isn't the best way to do it, however.


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