I feel we can close a discission at that point - we disagree which
approach is better, and there is no sense to continue dancing around.
I see only two technical issues here which differs:
1. You believe your GCC experts, I trust HW Architecture manual and
don't trust toolchain people too much ==> we see a different value in
fact that your approach has a subset of emulated ISAs (and it can't, of
course, emulate anything because some custom opcodes are reused).
2. My approach is ready to use and is used right now, you still have a
framework which passed an initial boot.
On 12/03/2014 05:29 PM, David Daney wrote:
On 12/03/2014 04:52 PM, Leonid Yegoshin wrote:
On 12/03/2014 04:20 PM, David Daney wrote:
It is a proof of concept. R6 can easily be added if needed.
Your XOL emulation doesn't handle R6 either, so this is no worse than
your patch in that respect.
You probably didn't research it well. A lot of changes in
arch/mips/kernel/branch.c and and arch/mips/math-emu/cp1emu.c, all of it
related with R6.
I looked at:
And I saw no R6 support.
Is it there, or in some other branch that isn't merged?
Sorry, I misunderstood your statement:
Yes, my "MIPS: Setup an instruction emulation in VDSO protected page
instead of user stack <http://patchwork.linux-mips.org/patch/8631/>" has
no any MIPS R6 specifics and actually has no any another MIPS Rx
specific or FPU specific besides the fact that emulation can be done by
multiple emulators and a small stack is supported in so-called "VDSO"
page. I just remember that I pointed you to place where MIPS R6 is done
and it has a lot of MIPS R6 instruction emulation and confused both events.