Re: DRAM unreliable under specific access patern
From: Pavel Machek
Date: Wed Dec 24 2014 - 11:46:09 EST
(I added original researches to the list).
I see you have FPGA-based detector, and probably PC based detector,
too. Would it be possible to share sources of the PC based one?
On Wed 2014-12-24 17:38:23, Pavel Machek wrote:
> It seems that it is easy to induce DRAM bit errors by doing repeated
> reads from adjacent memory cells on common hw. Details are at
> . Older memory modules seem to work better, and ECC should detect
> this. Paper has inner loop that should trigger this.
> Workarounds seem to be at hardware level, and tricky, too.
> Does anyone have implementation of detector? Any ideas how to work
> around it in software?
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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