Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource
From: Peter De Schrijver
Date: Thu Feb 12 2015 - 08:55:17 EST
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
> From: Tuomas Tynkkynen <ttynkkynen@xxxxxxxxxx>
> The DFLL is the main clocksource for the fast CPU cluster on Tegra124
> and also provides automatic CPU rail voltage scaling as well. The DFLL
> is a separate IP block from the usual Tegra124 clock-and-reset
> controller, so it gets its own node in the device tree.
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