Re: [PATCH 2/3] clk: divider: fix selection of divider when rounding to closest

From: Maxime Coquelin
Date: Mon Feb 23 2015 - 04:47:22 EST

Hello Uwe,

On 02/21/2015 11:40 AM, Uwe Kleine-KÃnig wrote:
It's an invalid approach to assume that among two divider values
the one nearer the exact divider is the better one.

Assume a parent rate of 1000 Hz, a divider with CLK_DIVIDER_POWER_OF_TWO
and a target rate of 89 Hz. The exact divider is ~ 11.236 so 8 and 16
are the candidates to choose from yielding rates 125 Hz and 62.5 Hz
respectivly. While 8 is nearer to 11.236 than 16 is, the latter is still
the better divider as 62.5 is nearer to 89 than 125 is.

Fixes: 774b514390b1 (clk: divider: Add round to closest divider)
Signed-off-by: Uwe Kleine-KÃnig <u.kleine-koenig@xxxxxxxxxxxxxx>
drivers/clk/clk-divider.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

For this one too, you can add my:
Acked-by: Maxime Coquelin <maxime.coquelin@xxxxxx>

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