On Tue, Mar 10, 2015 at 02:35:12PM +0000, Sudeep Holla wrote:
My initial assumption was that it will be NULL for Intel processors
and hence I assigned cacheinfo->priv to nb pointer unconditionally. So
I don't have any strong opinion here.
Right, we need the NB descriptor on AMD to do L3-specific operations,
see amd_l3_disable_index() for an example.
IOW, I ended up committing this:
From: Sudeep Holla <sudeep.holla@xxxxxxx>
Date: Wed, 11 Mar 2015 11:54:29 +0100
Subject: [PATCH] x86/cacheinfo: Fix cache_get_priv_group() for Intel
The private pointer provided by the cacheinfo code is used to implement
the AMD L3 cache-specific attributes using a pointer to the northbridge
descriptor. It is needed for performing L3-specific operations and for
that we need a couple of PCI devices and other service information, all
contained in the northbridge descriptor.
However, it's populated even on Intel processors for an L3 cache.