Re: [PATCH] Revert "MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction"

From: David Daney
Date: Wed Mar 11 2015 - 12:51:28 EST

On 03/11/2015 01:28 AM, Markos Chandras wrote:
On 02/23/2015 10:52 PM, David Daney wrote:
From: David Daney <david.daney@xxxxxxxxxx>

This reverts commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed.

There are two problems:

1) It breaks OCTEON, which will now crash in early boot with:

Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)

2) The logic is broken.

The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction
is required. The offending patch attempts (and fails) to change the
meaning to be that EHB is part of the ISA.

Signed-off-by: David Daney <david.daney@xxxxxxxxxx>

First of all sorry about the octeon breakage.

However, whilst this patch will fix Octeon it will break R6

But breaking R6 is not a regression, breaking OCTEON is. For new code, there is this bit of asymmetry.

Can we please consider another patch that will simply use
cpu_has_mips_r2_r6 instead of cpu_has_mips_r2 so both will work in 4.0?

If you have a patch that fixes the problem properly, please post it for consideration.

David Daney

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