Re: PCID and TLB flushes (was: [GIT PULL] kdbus for 4.1-rc1)

From: Andy Lutomirski
Date: Tue Apr 28 2015 - 19:23:58 EST

On Tue, Apr 28, 2015 at 4:16 PM, Linus Torvalds
<torvalds@xxxxxxxxxxxxxxxxxxxx> wrote:
> On Tue, Apr 28, 2015 at 3:54 PM, Andy Lutomirski <luto@xxxxxxxxxxxxxx> wrote:
>> I had a totally different implementation idea in mind. It goes
>> something like this:
>> For each CPU, we allocate a fixed number of PCIDs, e.g. 0-7. We have
>> a per-cpu array of the mm [1] that owns each PCID. [...]
> We've done this before on other architectures. See for example alpha.
> Look up "__get_new_mm_context()" and friends. I think sparc does the
> same (and I think sparc copied a lot of it from the alpha
> implementation).
> Iirc, the alpha version just generates a (per-cpu) asid one at a time,
> and has a generation counter so that when you run out of ASID's you do
> a global TLB invalidate on that CPU and start from 0 again. Actually,
> I think the generation number is just the high bits of the asid
> counter (alpha calls them "asn", intel calls them "pcid", and I tend
> to prefer "asid", but it's all the same thing).
> Then each thread just has a per-thread ASID. We don't try to make that
> be per-thread and per-cpu, but instead just force a new allocation
> when a thread moves to another CPU.

Alpha appears to have a per-thread per-cpu id of some sort:

/* The alpha MMU context is one "unsigned long" bitmap per CPU */
typedef unsigned long mm_context_t[NR_CPUS];

I think we can do it without that by keeping the mapping in reverse as
I sort of outlined -- for each cpu, store a mapping from mm to pcid.
When things fall out of the list, no big deal.

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