Re: [PATCH 4/8] ARCv2: perf: Support sampling events using overflow interrupts

From: Vineet Gupta
Date: Tue Jun 16 2015 - 01:37:59 EST

On Monday 15 June 2015 09:55 PM, Peter Zijlstra wrote:
> On Tue, Jun 09, 2015 at 05:49:28PM +0530, Vineet Gupta wrote:
>> + if (arc_pmu->has_interrupts) {
>> + int irq = platform_get_irq(pdev, 0);
> Hmm, so you're requesting a regular interrupt.
> I see your architecture has IRQ priorities, could you play games and
> create NMIs using those?
> For example, never mask L1 (assuming that's the highest priority) and
> treat that as an NMI.

I've had this idea before, however, while ARCv2 provides hardware interrupt
priorities, we really can't implement true NMI, because CLRI / SETI used at
backend of loal_irq_save() / restore() impact all priorities (statsu32 register
has a global enable interrupt bit which these wiggle). So e.g. a
spin_lock_irqsave() will lock out even the perf interrupt.

OTOH, we can improve the perf isr path a bit - by not routing it thru regular
interrupt return path (song and dance of CONFIG_PREEMPT_IRQ and possible
preemption). Plus there's a bit more we can do in the isr itself - not looping
thru 32 counters etc using ffs() etc - but I'd rather do that as separate series,
once we have the core support in.


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