Re: [PATCH v3 2/3] clk: stm32: Add clock driver for STM32F4[23]xxx devices

From: Daniel Thompson
Date: Tue Jun 23 2015 - 04:25:35 EST

On 23/06/15 00:21, Stephen Boyd wrote:
On 06/10, Daniel Thompson wrote:
The driver supports decoding and statically modelling PLL state (i.e.
we inherit state from bootloader) and provides support for all
peripherals that support simple one-bit gated clocks. The covers all
peripherals whose clocks come from the AHB, APB1 or APB2 buses.

It has been tested on an STM32F429I-Discovery board. The clock counts
for TIM2, USART1 and SYSTICK are all set correctly and the wall clock
looks OK when checked with a stopwatch. I have also tested a prototype
driver for the RNG hardware. The RNG clock is correctly enabled by the
framework (also did inverse test and proved that by changing DT to
configure the wrong clock bit then we observe the RNG driver to fail).

Signed-off-by: Daniel Thompson <daniel.thompson@xxxxxxxxxx>
Reviewed-by: Maxime Coquelin <mcoquelin.stm32@xxxxxxxxx>

I also squashed in some sparse fixes. Please check.

That was extremely generous! Thanks.

The changes all eyeball OK but I'll double check things tonight just in case.


To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at
Please read the FAQ at