Re: [PATCH v1 4/7] ARM: dts: apq8064: Add MDP support

[Rob Clark]

On Tue, Jul 28, 2015 at 1:31 PM, Andreas FÃrber <afaerber@xxxxxxx> wrote:
> Hi,
>
> Am 28.07.2015 um 14:54 schrieb Srinivas Kandagatla:
>> From: Rob Clark <robdclark@xxxxxxxxx>
>>
>> This patch adds MDP node to APQ8064 dt.
>>
>> Signed-off-by: Rob Clark <robdclark@xxxxxxxxx>
>> [Srinivas Kandagatla] : updated with new style rpm regulators
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
>> ---
>>  arch/arm/boot/dts/qcom-apq8064.dtsi | 87 +++++++++++++++++++++++++++++++++++++
>>  1 file changed, 87 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
>> index cba4ccb..7d2cc45 100644
>> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
>> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> [...]
>> +             gpu: qcom,adreno-3xx@4300000 {
>> +                     compatible = "qcom,adreno-3xx";
>
> I thought that wildcards were forbidden in compatible strings? Then this
> should be replaced by the real number, with a fallback to the first
> compatible one.

That would at least result in a big number of different compatibles,
esp. when you consider patchlevels of the different gpu's, which in
some cases needs to be known (esp. to userspace).. ie. a320.0 is not
the same thing as a320.2.  And the "real numbers" themselves are
confusing as a result of meddling by marketeers.. (ie. a305 vs a305b
vs a306.. which actually map to 305.x, 306.x and 307.x).  The current
scheme is easy to figure out how to setup the dt nodes, ie. easy to
know a3xx vs a4xx, and then copy the chipid property from downstream
dt, and everything works.

The current scheme groups by major gpu revision (ie. things where
basically all the registers change, ie. a3xx/a4xx/a5xx) with using
chipid and a few if statements here and there (kernel and userspace)
to deal with the intra-generation differences.  (The chipid is
something which in theory should be read out of a version register,
but seems that cannot be trusted.)

Not to mention that a3xx/a4xx/etc is how userspace code in mesa is partitioned.

BR,
-R

> And can't we just name the node qcom,adreno without version suffix?
>
> Regards,
> Andreas
>
>> +                     reg = <0x04300000 0x20000>;
>> +                     reg-names = "kgsl_3d0_reg_memory";
>> +                     interrupts = <GIC_SPI 80 0>;
>> +                     interrupt-names = "kgsl_3d0_irq";
>> +                     clock-names =
>> +                         "core_clk",
>> +                         "iface_clk",
>> +                         "mem_clk",
>> +                         "mem_iface_clk";
>> +                     clocks =
>> +                         <&mmcc GFX3D_CLK>,
>> +                         <&mmcc GFX3D_AHB_CLK>,
>> +                         <&mmcc GFX3D_AXI_CLK>,
>> +                         <&mmcc MMSS_IMEM_AHB_CLK>;
>> +                     qcom,chipid = <0x03020002>;
>> +                     qcom,gpu-pwrlevels {
>> +                             compatible = "qcom,gpu-pwrlevels";
>> +                             qcom,gpu-pwrlevel@0 {
>> +                                     qcom,gpu-freq = <450000000>;
>> +                             };
>> +                             qcom,gpu-pwrlevel@1 {
>> +                                     qcom,gpu-freq = <27000000>;
>> +                             };
>> +                     };
>> +             };
>> +
>> +             mdp: qcom,mdp@5100000 {
>> +                     compatible = "qcom,mdp";
>> +                     reg = <0x05100000 0xf0000>;
>> +                     interrupts = <GIC_SPI 75 0>;
>> +                     connectors = <&hdmi>;
>> +                     gpus = <&gpu>;
>> +                     clock-names =
>> +                         "core_clk",
>> +                         "iface_clk",
>> +                         "lut_clk",
>> +                         "src_clk",
>> +                         "hdmi_clk",
>> +                         "mdp_clk",
>> +                         "mdp_axi_clk";
>> +                     clocks =
>> +                         <&mmcc MDP_CLK>,
>> +                         <&mmcc MDP_AHB_CLK>,
>> +                         <&mmcc MDP_LUT_CLK>,
>> +                         <&mmcc TV_SRC>,
>> +                         <&mmcc HDMI_TV_CLK>,
>> +                         <&mmcc MDP_TV_CLK>,
>> +                         <&mmcc MDP_AXI_CLK>;
>> +             };
>>       };
>>  };
>
> --
> SUSE Linux GmbH, Maxfeldstr. 5, 90409 NÃrnberg, Germany
> GF: Felix ImendÃrffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB
> 21284 (AG NÃrnberg)
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