Re: [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk

From: Stephen Boyd
Date: Tue Aug 11 2015 - 19:54:57 EST

On 07/24, dinguyen@xxxxxxxxxxxxxxxxxxxxx wrote:
> From: Dinh Nguyen <dinguyen@xxxxxxxxxxxxxxxxxxxxx>
> The debug base clock can be bypassed from the main PLL to the OSC1 clock.
> The bypass register is the staysoc1(0x10) register that is in the clock
> manager.
> This patch adds the option to get the correct parent for the debug base
> clock.
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxxxxxxxxxxxxx>
> ---

Applied to clk-next

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