Re: [RFC PATCH] drm/i915: PSR regressions on Broadwell
From: Brian Norris
Date: Mon Sep 28 2015 - 17:08:11 EST
On Mon, Sep 28, 2015 at 10:14:04AM +0300, Jani Nikula wrote:
> On Sat, 26 Sep 2015, Brian Norris <briannorris@xxxxxxxxxxxx> wrote:
> > When using PSR, I see the screen freeze after only a few frames (sometimes a
> > split second; sometimes it seems like practically the first frame). Bisecting
> > led me to commit 3301d4092106 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT
> > logic") in v4.2. This patch is the simplest fix that gets it working again for
> > me, but it's probably wrong.
> > Random thought: perhaps my panel's DPCD is programmed incorrectly?
> > Anyway, any tips on fixing this properly?
> Here's a thought:
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index a04b4dc5ed9b..3a911d4a2308 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -274,6 +274,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> idle_frames += 4;
> + idle_frames = clamp(idle_frames, 0, 15);
> I915_WRITE(EDP_PSR_CTL(dev), val |
> (IS_BROADWELL(dev) ? 0 : link_entry_time) |
> max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
No dice. The VBT actually gives 0, so I just end up with the default 5 +
4 either way.
> We do clamp the VBT value to range 0..15, but then go on to add to it.
But this patch seems quite reasonable anyway.
Acked-by: Brian Norris <briannorris@xxxxxxxxxxxx>
> Otherwise, up to Rodrigo I guess.
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