Re: [PATCH] x86: Use entire page for the per-cpu GDT only if paravirt-enabled

From: H. Peter Anvin
Date: Tue Sep 29 2015 - 22:27:42 EST

No, it is a natural result of an implemention which treats setting the A bit as an abnormal flow (e.g. in microcode as opposed to hardware).

On September 29, 2015 7:11:59 PM PDT, ebiederm@xxxxxxxxxxxx wrote:
>"H. Peter Anvin" <hpa@xxxxxxxxx> writes:
>> On 09/29/2015 06:20 PM, Eric W. Biederman wrote:
>>> Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> writes:
>>>> On Tue, Sep 29, 2015 at 1:35 PM, Andy Lutomirski
><luto@xxxxxxxxxxxxxx> wrote:
>>>>> Does anyone know what happens if you stick a non-accessed segment
>>>>> the GDT, map the GDT RO, and access it?
>>>> You should get a #PF, as you guess, but go ahead and test it if you
>>>> want to make sure.
>>> I tested this by accident once when workinng on what has become
>>> as coreboot. Early in boot with your GDT in a EEPROM switching from
>>> real mode to 32bit protected mode causes a write and locks up the
>>> machine when the hardware declines the write to the GDT to set the
>>> accessed bit. As I recall the write kept being retried and retried
>>> retried...
>>> Setting the access bit in the GDT cleared up the problem and I did
>>> look back.
>>> Way up in 64bit mode something might be different, but I don't know
>>> cpu designeres would waste the silicon.
>> This is totally different from a TLB violation. In your case, the
>> goes through as far as the CPU is concerned, but when the data is
>> fetched back, it hasn't changed. A write to a TLB-protected location
>> will #PF.
>The key point is that a write is generated when the cpu needs to set
>access bit. I agree the failure points are different. A TLB fault vs
>case where the hardware did not accept the write.
>The idea of a cpu reading back data (and not trusting it's cache
>coherency controls) to verify the access bit gets set seems mind
>boggling. That is slow, stupid, racy and incorrect. Incorrect as the
>cpu should not only set the access bit once per segment register load.
>In my case I am pretty certain it was something very weird with the
>hardware not acceppting the write and either not acknowledging the bus
>transaction or cancelling it. In which case the cpu knew the write had
>not made it to the ``memory'' and was trying to cope.

Sent from my Android device with K-9 Mail. Please excuse my brevity.
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