Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support

[Geert Uytterhoeven]

Hi Laurent,

On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart
<laurent.pinchart@xxxxxxxxxxxxxxxx> wrote:
> On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote:
>> Amend the DT bindings to include the optional clock sources for the Baud
>> Rate Generator for External Clock (BRG), as found on some SCIF variants
>> and on HSCIF.

>> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> @@ -46,6 +46,12 @@ Required properties:
>>      On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>>        - "hsck" for the optional external clock input (on HSCIF),
>>        - "sck" for the optional external clock input (on other variants).
>> +    On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
>> +    (some SCIF and HSCIF), additional clocks may be specified:
>> +      - "int_clk" for the optional internal clock source for the frequency
>> +     divider (typically the (AXI or SHwy) bus clock),
>
> Isn't this always the same clock as the SCIF functional clock ?

(On R-Car Gen2/3)

No, SCIF uses different parents for fck (p) and int_clk (zs).
HSCIF uses the same parents though (zs).

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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