Re: [PATCH 1/3] ata: sata_dwc_460ex: use "dmas" DT property to find dma channel

[Måns Rullgård]

Andy Shevchenko <andy.shevchenko@xxxxxxxxx> writes:

> On Sun, Dec 20, 2015 at 7:11 PM, Måns Rullgård <mans@xxxxxxxxx> wrote:
>> Julian Margetson <runaway@xxxxxxxx> writes:
>>
>>> On 12/19/2015 4:41 PM, Måns Rullgård wrote:
>>>> Andy Shevchenko <andy.shevchenko@xxxxxxxxx> writes:
>>>>
>>>>> On Sat, Dec 19, 2015 at 10:16 PM, Julian Margetson <runaway@xxxxxxxx> wrote:
>>>>>> On 12/19/2015 3:07 PM, Måns Rullgård wrote:
>>>>>>> Julian Margetson <runaway@xxxxxxxx> writes:
>
>>> [   18.606292] dma dma0chan0: dwc_tx_submit: queued 2
>>> [   18.611091] dma dma0chan0: dwc_dostart_first_queued: started 2
>>> [   48.748614] ata3: lost interrupt (Status 0x40)
>>
>> Now we're getting somewhere.  The dma transfer is set up and initiated,
>> but then nothing happens.  Comparing the old sata_dwc driver, from
>> before the switch to dmaengine, with the dw_dma driver, I noticed an
>> obvious problem: the descriptors are filled in using the wrong byte
>> order.
>
> So, it means we have IO in little endian, but DMA reads data from
> memory in big endian?

No, it means the IO is little endian, and the DMA reads from memory in
little endian while the host CPU is big endian.

>>  This patch might fix that.
>
> In case it works I have to test it on AVR32.

Unless I made a mistake, there should be no difference there.  Still got
to test it of course.

-- 
Måns Rullgård
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