Re: [RFC 09/13] x86/mm: Disable interrupts when flushing the TLB using CR3

[Andy Lutomirski]

On Wed, Jan 13, 2016 at 3:43 PM, Dave Hansen
<dave.hansen@xxxxxxxxxxxxxxx> wrote:
> On 01/13/2016 03:35 PM, Andy Lutomirski wrote:
>> Can anyone here ask a hardware or microcode person what's going on
>> with CR3 writes possibly being faster than INVPCID?  Is there some
>> trick to it?
>
> I just went and measured it myself this morning.  "INVPCID Type 3" (all
> contexts no global) on a Skylake system was 15% slower than a CR3 write.
>
> Is that in the same ballpark from what you've observed?
>
>

It's similar, except that I was comparing "INVPCID Type 1" (single
context no globals) to a CR3 write.

Type 2, at least, is dramatically faster than the pair of CR4 writes
it replaces.

--Andy