On Thu, Jan 14, 2016 at 03:33:40PM -0800, Leonid Yegoshin wrote:
Don't be fooled here by words "ordered" and "completed" - it is HWSo smp_mb() can be SYNC_MB. However, mb() needs to be SYNC for MMIO
design items and actually written poorly.
Just assume that SYNC_MB is absolutely the same as SYNC for any CPU
and coherent device (besides performance). The difference can be in
non-coherent devices because SYNC actually tries to make a barrier
for them too. In some SoCs it is just the same because there is no
need to barrier a non-coherent device (device register access
usually strictly ordered... if there is no bridge in between).
Note: I am not sure about ANY past MIPS R2 CPU because that stuff isSo you need to build a different kernel for some types of MIPS systems?
implemented some time but nobody made it in Linux kernel (it was
used by some vendor for non-Linux system). For that reason my patch
for lightweight SYNCs has an option - implement it or implement a
generic SYNC. It is possible that some vendor did it in different
way but nobody knows or test it. But as a minimum - SYNC must be
implemented in spinlocks/atomics/bitops, in recent P5600 it is
proven that read can pass write in atomics.
MIPS R6 is a different story, I verified lightweight SYNCs from the
beginning and it also should use SYNCs.
Or do you do boot-time rewriting, like a number of other arches do?