[PATCH 4.2.y-ckt 156/305] cxl: Set endianess of kernel contexts

From: Kamal Mostafa
Date: Fri Jan 15 2016 - 19:51:05 EST

4.2.8-ckt2 -stable review patch. If anyone has any objections, please let me know.


From: Frederic Barrat <fbarrat@xxxxxxxxxxxxxxxxxx>

commit e606e035cc7293a3824527d97359711fdda00663 upstream.

A process element (defined in CAIA) keeps track of the endianess of
contexts through the Little Endian (LE) bit of the State Register. It
is currently set for user contexts, but was somehow forgotten for
kernel contexts, so this patch fixes it.
It could lead to erratic behavior from an AFU when the context is
attached through the kernel API.

Fixes: 2f663527bd6a ("cxl: Configure PSL for kernel contexts and merge code")
Signed-off-by: Frederic Barrat <fbarrat@xxxxxxxxxxxxxxxxxx>
Suggested-by: Michael Neuling <mikey@xxxxxxxxxxx>
Signed-off-by: Michael Ellerman <mpe@xxxxxxxxxxxxxx>
Signed-off-by: Kamal Mostafa <kamal@xxxxxxxxxxxxx>
drivers/misc/cxl/native.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 8339eb2..b703559 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/misc/cxl/native.c
@@ -434,6 +434,7 @@ static u64 calculate_sr(struct cxl_context *ctx)
u64 sr = 0;

+ set_endian(sr);
if (ctx->master)
sr |= CXL_PSL_SR_An_MP;
if (mfspr(SPRN_LPCR) & LPCR_TC)
@@ -443,7 +444,6 @@ static u64 calculate_sr(struct cxl_context *ctx)
sr |= CXL_PSL_SR_An_HV;
} else {
- set_endian(sr);
sr &= ~(CXL_PSL_SR_An_HV);
if (!test_tsk_thread_flag(current, TIF_32BIT))
sr |= CXL_PSL_SR_An_SF;