On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdegoede@xxxxxxxxxx> wrote:
On 21-01-16 06:26, Chen-Yu Tsai wrote:
According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
instance can use eMMC hardware reset.
This is going to need some more explanation, does this mean
that the old dtsi is wrong and the emmc does not work there are all ?
mmc2 works fine for either 4 bit SDR/DDR or 8 bit SDR only. It does
not work for 8 bit DDR. I actually tested all the above combinations.
Also see https://groups.google.com/d/msg/linux-sunxi/pMzwMWwLALw/6WGgCN1eAQAJ
About old DTs not working:
a) The old DT will not work with the mmc patches, as it will try 8 bit DDR
and fail. Also, the old DT does not use the highest drive strength for
the mmc pins, meaning it might not work for the other chip families.
b) Old DT + old kernel works fine (8 bit high-speed), just slower.
An alternative would be to drop MMC_CAP_1_8V_DDR from the driver, and
use the "mmc-ddr-1_8v" DT capability flag at the dtsi or board level.
There's no real way to describe "don't use 8 bit with MMC DDR" in the DT.
Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx>
arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
index ea69fb8ad4d8..4ec0c8679b2e 100644
@@ -61,12 +61,14 @@
/* eMMC on core board */
pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+ pinctrl-0 = <&mmc3_8bit_emmc_pins>;
vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
bus-width = <8>;
status = "okay";