[PATCH v3 0/3] x86/mm: INVPCID support
From: Andy Lutomirski
Date: Fri Jan 29 2016 - 14:43:42 EST
Boris, I think you already have these prerequisites queued up:
This is a straightforward speedup on Ivy Bridge and newer, IIRC.
(I tested on Skylake. INVPCID is not available on Sandy Bridge.
I don't have Ivy Bridge, Haswell or Broadwell to test on, so I
could be wrong as to when the feature was introduced.)
I think we should consider these patches separately from the rest
of the PCID stuff -- they barely interact, and this part is much
simpler and is useful on its own.
Changes from v2:
- Add macros for the INVPCID mode numbers.
- Add a changelog message for the chicken bit.
v1 was exactly identical to patches 2-4 of the PCID RFC series.
Andy Lutomirski (3):
x86/mm: Add INVPCID helpers
x86/mm: Add a noinvpcid option to turn off INVPCID
x86/mm: If INVPCID is available, use it to flush global mappings
Documentation/kernel-parameters.txt | 2 ++
arch/x86/include/asm/tlbflush.h | 57 +++++++++++++++++++++++++++++++++++++
arch/x86/kernel/cpu/common.c | 16 +++++++++++
3 files changed, 75 insertions(+)