Re: [PATCH v6 1/8] Documentation: arm: define DT cpu capacity-dmips-mhz bindings

From: Rob Herring
Date: Wed Jul 20 2016 - 14:56:14 EST

On Tue, Jul 19, 2016 at 01:40:41PM +0100, Juri Lelli wrote:
> ARM systems may be configured to have cpus with different power/performance
> characteristics within the same chip. In this case, additional information
> has to be made available to the kernel (the scheduler in particular) for it
> to be aware of such differences and take decisions accordingly.
> Therefore, this patch aims at standardizing cpu capacities device tree
> bindings for ARM platforms. Bindings define cpu capacity-dmips-mhz
> parameter, to allow operating systems to retrieve such information from
> the device tree and initialize related kernel structures, paving the way
> for common code in the kernel to deal with heterogeneity.
> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> Cc: Pawel Moll <pawel.moll@xxxxxxx>
> Cc: Mark Rutland <mark.rutland@xxxxxxx>
> Cc: Ian Campbell <ijc+devicetree@xxxxxxxxxxxxxx>
> Cc: Kumar Gala <galak@xxxxxxxxxxxxxx>
> Cc: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx>
> Cc: Olof Johansson <olof@xxxxxxxxx>
> Cc: Gregory CLEMENT <gregory.clement@xxxxxxxxxxxxxxxxxx>
> Cc: Paul Walmsley <paul@xxxxxxxxx>
> Cc: Linus Walleij <linus.walleij@xxxxxxxxxx>
> Cc: Chen-Yu Tsai <wens@xxxxxxxx>
> Cc: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Signed-off-by: Juri Lelli <juri.lelli@xxxxxxx>
> ---
> Changes from v1:
> - removed section regarding capacity-scale
> - added information regarding normalization
> Changes from v4:
> - binding changed to capacity-dmips-mhz
> - sections and changelod updated accordingly
> Changes from v5:
> - addressed Mark and Vincent comments
> ---
> .../devicetree/bindings/arm/cpu-capacity.txt | 236 +++++++++++++++++++++
> Documentation/devicetree/bindings/arm/cpus.txt | 10 +
> 2 files changed, 246 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/cpu-capacity.txt

I guess I'm okay with the scaled values, so:

Acked-by: Rob Herring <robh@xxxxxxxxxx>


> +Example 2 (ARM 32-bit, 4-cpu system, two clusters,
> + cpus 0,1@1GHz, cpus 2,3@500MHz):
> +capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first
> +cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency)

This example is a bit confusing with both the capacity and frequency
being half. I also find it a bit unrealistic to have a 2x performance
difference on the same micro arch. But it is all just an example...