[PATCH 4.6 094/203] drm/fsl-dcu: use flat regmap cache

From: Greg Kroah-Hartman
Date: Mon Jul 25 2016 - 17:35:43 EST

4.6-stable review patch. If anyone has any objections, please let me know.


From: Stefan Agner <stefan@xxxxxxxx>

commit ce492b3b8f99cf9d2f807ec22d8805c996a09503 upstream.

Using flat regmap cache instead of RB-tree to avoid the following
lockdep warning on driver load:
WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2755 lockdep_trace_alloc+0x15c/0x160()

The RB-tree regmap cache needs to allocate new space on first
writes. However, allocations in an atomic context (e.g. when a
spinlock is held) are not allowed. The function regmap_write
calls map->lock, which acquires a spinlock in the fast_io case.
Since the FSL DCU driver uses MMIO, the regmap bus of type
regmap_mmio is being used which has fast_io set to true.

Use flat regmap cache and specify max register to be large
enouth to cover all registers available in LS1021a and Vybrids
register space.

Signed-off-by: Stefan Agner <stefan@xxxxxxxx>
Cc: Mark Brown <broonie@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>

drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -40,9 +40,10 @@ static const struct regmap_config fsl_dc
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
- .cache_type = REGCACHE_RBTREE,
+ .cache_type = REGCACHE_FLAT,

.volatile_reg = fsl_dcu_drm_is_volatile_reg,
+ .max_register = 0x11fc,

static int fsl_dcu_drm_irq_init(struct drm_device *dev)