[PATCH v2 2/4] Add enabling of the R3 MWAIT during boot for KNL

From: Grzegorz Andrejczuk
Date: Wed Oct 12 2016 - 08:18:20 EST


If processor is Intel Xeon Phi we enable user-level mwait feature.
Enabling this feature suppreses invalid-opcode error, when MONITOR/MWAIT
is called from ring 3.

Change-Id: I1c7defb99296b022790a068a6c725b3e860cd68c
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@xxxxxxxxx>
---
arch/x86/kernel/cpu/intel.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcd484d..ac6df08 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -61,6 +61,14 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
}
}

+static int phir3mwait = 1;
+static int __init phir3mwait_disable(char *value)
+{
+ phir3mwait = 0;
+ return 1;
+}
+__setup("intel-phir3mwait=disable", phir3mwait_disable);
+
static void early_init_intel(struct cpuinfo_x86 *c)
{
u64 misc_enable;
@@ -211,6 +219,25 @@ static void early_init_intel(struct cpuinfo_x86 *c)
}

check_mpx_erratum(c);
+
+ /*
+ * Setting ring 3 MONITOR/MWAIT for all threads
+ * when CPU is Xeon Phi Family x200
+ * This can be disabled with phir3mwait=disable cmdline switch.
+ * We preserve the reserved values and set only 2nd bit.
+ * Ref:
+ * https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait
+ */
+ if (c->x86 == 6 &&
+ c->x86_model == INTEL_FAM6_XEON_PHI_KNL &&
+ phir3mwait) {
+ u64 prev;
+
+ rdmsrl(MSR_PHI_MISC_THD_FEATURE, prev);
+ if ((prev & MSR_PHI_MISC_THD_FEATURE_R3MWAIT) == 0)
+ wrmsrl(MSR_PHI_MISC_THD_FEATURE,
+ prev | MSR_PHI_MISC_THD_FEATURE_R3MWAIT);
+ }
}

#ifdef CONFIG_X86_32
--
2.5.1