Re: What exactly do 32-bit x86 exceptions push on the stack in the CS slot?

From: hpa
Date: Mon Nov 21 2016 - 00:53:36 EST

On November 19, 2016 5:52:57 PM PST, Andy Lutomirski <luto@xxxxxxxxxx> wrote:
>This is a question for the old-timers here, since I can't find
>anything resembling an answer in the SDM.
>Suppose an exception happens (#UD in this case, but I assume it
>doesn't really matter). We're not in long mode, and the IDT is set up
>to deliver to a normal 32-bit kernel code segment. We're running in
>that very same code segment when the exception hits, so no CPL change
>occurs and the TSS doesn't particularly matter.
>The CPU will push EFLAGS, CS, and RIP. Here's the question: what
>happens to the high word of CS on the stack?
>The SDM appears to say nothing at all about this. Modern systems
>(e.g. my laptop running in 32-bit legacy mode under KVM) appear to
>zero-extend CS. But Matthew's 486DX appears to put garbage in the
>high bits (or maybe just leave whatever was already on the stack in
>Do any of you happen to know what's going on and when the behavior
>changed? I'd like to know just how big of a problem this is. Because
>if lots of CPUs work like Matthew's, we have lots of subtle bugs on

I believe i686+ writes zero, older CPUs leave unchanged.
Sent from my Android device with K-9 Mail. Please excuse my brevity.