Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support
From: H. Peter Anvin
Date: Tue Dec 13 2016 - 17:51:02 EST
On 12/09/16 07:32, Kirill A. Shutemov wrote:
> Something like this?
> diff --git a/arch/x86/boot/cpuflags.c b/arch/x86/boot/cpuflags.c
> index 6687ab953257..366aad972025 100644
> --- a/arch/x86/boot/cpuflags.c
> +++ b/arch/x86/boot/cpuflags.c
> @@ -70,16 +70,22 @@ int has_eflag(unsigned long mask)
> # define EBX_REG "=b"
> -static inline void cpuid(u32 id, u32 *a, u32 *b, u32 *c, u32 *d)
> +static inline void cpuid_count(u32 id, u32 count,
> + u32 *a, u32 *b, u32 *c, u32 *d)
> + *a = id;
> + *c = count;
These two lines are wrong, remove them.
> asm volatile(".ifnc %%ebx,%3 ; movl %%ebx,%3 ; .endif \n\t"
> "cpuid \n\t"
> ".ifnc %%ebx,%3 ; xchgl %%ebx,%3 ; .endif \n\t"
> : "=a" (*a), "=c" (*c), "=d" (*d), EBX_REG (*b)
> - : "a" (id)
> + : "a" (id), "c" (count)
> +#define cpuid(id, a, b, c, d) cpuid_count(id, 0, a, b, c, d)
Other than that, it's correct.
That being said, the claim that ECX ought to be zeroed on a
non-subleaf-equipped CPUID leaf is spurious, in my opinion. That being
said, it also doesn't do any harm and might avoid problems in the
opposite direction, e.g. someone thinking that leaf 7 doesn't have
It might also be better to have something like:
#define SAVE_EBX(x) ".ifnc %%ebx," x "; movl %%ebx," x "; .endif"
#define SWAP_EBX(x) ".ifnc %%ebx," x "; xchgl %%ebx," x "; .endif"
... but if it is only used once it might just be more confusion.