Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers
From: Linus Walleij
Date: Tue Dec 27 2016 - 17:16:58 EST
On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery <andrew@xxxxxxxx> wrote:
> The System Control Unit IP block in the Aspeed SoCs is typically where
> the pinmux configuration is found, but not always. A number of pins
> depend on state in one of LPC Host Control (LHC) or SoC Display
> Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
> means to adjust these as necessary.
> We use syscon to cast a regmap over the GFX and LPC blocks, which is
> used as an arbitration layer between the relevant driver and the pinctrl
> subsystem. The regmaps are then exposed to the SoC-specific pinctrl
> drivers by phandles in the devicetree, and are selected during a mux
> request by querying a new 'ip' member in struct aspeed_sig_desc.
> Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx>
> Reviewed-by: Joel Stanley <joel@xxxxxxxxx>
Patch applied, adding Rob's ack in the process.