+ tmp = (unsigned long long)clk_get_rate(pc->clk) * period_ns;
+ do_div(tmp, 1000000000);
+ period = tmp;
+ tmp = (unsigned long long)period * duty_ns;
+ do_div(tmp, period_ns);
+ duty = period - tmp;
+ if (duty >= period)
+ duty = period - 1;
+ if (duty >> 24 || period >> 24)
+ return -EINVAL;
+ chan->period_ns = period_ns;
+ chan->duty_ns = duty_ns;
+ writel(duty, pc->base + PWM_HRC(pwm->hwpwm));
+ writel(period, pc->base + PWM_LRC(pwm->hwpwm));
+ writel(0x00, pc->base + PWM_CNT(pwm->hwpwm));
PWM_HRC and PWM_LRC names suggest that you're using high/low state
counters here rather than duty/period - but with no documentation
I'm just guessing here.
Indeed, the high/low state counters is used here.
Change the name to duty_cnt/period_cnt.