On Fri, 2017-02-17 at 11:47 +0100, Philipp Zabel wrote:
On Wed, 2017-02-15 at 18:19 -0800, Steve Longerbeam wrote:
+static void csi2_dphy_init(struct csi2_dev *csi2)
+ * FIXME: 0x14 is derived from a fixed D-PHY reference
+ * clock from the HSI_TX PLL, and a fixed target lane max
+ * bandwidth of 300 Mbps. This value should be derived
If the table in https://community.nxp.com/docs/DOC-94312 is correct,
this should be 850 Mbps. Where does this 300 Mbps value come from?
I got it, the dptdin_map value for 300 Mbps is 0x14 in the Rockchip DSI
driver. But that value is written to the register as HSFREQRANGE_SEL(x):
#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
which is 0x28. Further, the Rockchip D-PHY probably is another version,
as its max_mbps goes up to 1500.