Re: [PATCH] perf/x86: fix event counter update issue
From: Andi Kleen
Date: Wed Feb 22 2017 - 14:19:21 EST
> No. It related to the counter width. The number of bits we can use should be
> 1 bit less than the total width. Otherwise, there will be problem.
> For big cores such as haswell, broadwell, skylake, the counter width is 48 bit.
> So we can only use 47 bits.
> For Silvermont and KNL, the counter width is only 32 bit I think. So we can only
> use 31 bits.
It is 40 bits on these cores, so 39bits.