On Mon, Feb 20, 2017 at 11:09:43AM +0000, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:Agreed. I'd also go a step further and say that for PMUs with either
The L3 cache PMU use N-N SPI interrupt which has no supportCould you elaborate on what you mean by this?
in kernel mainline.
I don't understand what is meant here. How exactly are the interrupts
wired up in HW, and what exactly is not supported by Linux?
So use hrtimer to poll and update eventI'm not too keen on giving userspace the ability to control this, since
counter to avoid overflow condition for L3 cache PMU.
A interval of 10 seconds is used for the hrtimer.
The time interval can be configured in the sysfs.
it gives an awful lot of rope for userspace to tie around itself.
terminally broken interrupts (like this one) or just missing interrupts
(like the CPU PMU on raspberry pi iirc), then the perf core should take
care of an hrtimer in an attempt to generate samples often enough. We
already have PERF_PMU_CAP_NO_INTERRUPT, but it currently just disables
The fiddly part is knowing how to program the timer, and I think you'd
need the PMU driver to provide an upper-bound on events per nanosecond.
I'm pretty sure that would be highly unreliable (especially for shared
resources such as the L3), at which point, is it worth the hassle?