Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

[matthew . gerlach]

On Mon, 27 Feb 2017, Rob Herring wrote:

Hi Rob,


> On Wed, Feb 15, 2017 at 01:10:37PM -0800, matthew.gerlach@xxxxxxxxxxxxxxx wrote:
> > From: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
> >
> > Device Tree bindings for Altera Partial Reconfiguraion IP?
> >
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
> > ---
> >  Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> >
> > diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> > new file mode 100644
> > index 0000000..ada821f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> > @@ -0,0 +1,12 @@
> > +Altera Partial Reconfiguration IP
> > +
> > +Required properties:
> > +- compatible : should contain "altr,pr-ip"
>
> Kind of generic. There's only one version of h/w?


Fair point on being generic.  It does match the published documentation, 
but we could be more specific with "altr,a10-pr-ip" because it 
really is only for an Arria10.

Matthew Gerlach

> > +- reg        : base address and size for memory mapped io.
> > +
> > +Example:
> > +
> > +	fpga_mgr: fpga-mgr@ff20c000 {
> > +		compatible = "altr,pr-ip";
> > +		reg = <0xff20c000 0x10>;
> > +	};
> > --
> > 2.7.4