Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable
From: Peter De Schrijver
Date: Thu May 04 2017 - 03:42:43 EST
On Fri, Apr 21, 2017 at 07:38:48PM -0700, Stephen Boyd wrote:
> On 04/20, Peter De Schrijver wrote:
> > PLL SS was only controlled when setting the PLL rate, not when the PLL
> > itself is enabled or disabled. This means that if the PLL rate was set
> > before the PLL is enabled, SS will not be enabled, even when configured.
> > Signed-off-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
> Fixes tag? Or this isn't a problem right now, just future fix?
This isn't a problem right now, at least noone complained about it.