Re: [PATCH 5/7] clk: mvebu: cp110: add sdio clock to cp-110 system controller
From: Rob Herring
Date: Tue May 23 2017 - 11:23:49 EST
On Fri, May 19, 2017 at 05:55:23PM +0200, Gregory CLEMENT wrote:
> From: Konstantin Porotchkin <kostap@xxxxxxxxxxx>
> This commit updates the CP110 system controller driver to add the
> definition for a missing clock.
> The SDIO clock is dedicated driving the SDHCI interface and its frequency
> is 400MHz (2/5 of PLL source clock).
> The SDIO interface should be bound to this clock and not the core clock
> as in the older code.
> Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
> the HW really supports up to 400 Mhz.
> This patch also fixes the NAND clock relationship documentation.
> Signed-off-by: Konstantin Porotchkin <kostap@xxxxxxxxxxx>
> - use sdio instead of emmc to name the clock
> - update binding documentation]
> Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxxxxxxxxx>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxxxxxxxxx>
> Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 1 +
> drivers/clk/mvebu/cp110-system-controller.c | 28 +++++++++++++++++++++++-----
> 2 files changed, 24 insertions(+), 5 deletions(-)
Acked-by: Rob Herring <robh@xxxxxxxxxx>