Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID
From: Andy Lutomirski
Date: Thu Jun 22 2017 - 23:09:56 EST
On Thu, Jun 22, 2017 at 2:22 PM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
> On Thu, 22 Jun 2017, Andy Lutomirski wrote:
>> On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
>> > Now one other optimization which should be trivial to add is to keep the 4
>> > asid context entries in cpu_tlbstate and cache the last asid in thread
>> > info. If that's still valid then use it otherwise unconditionally get a new
>> > one. That avoids the whole loop machinery and thread info is cache hot in
>> > the context switch anyway. Delta patch on top of your version below.
>> I'm not sure I understand. If an mm has ASID 0 on CPU 0 and ASID 1 on
>> CPU 1 and a thread in that mm bounces back and forth between those
>> CPUs, won't your patch cause it to flush every time?
> Yeah, I was too focussed on the non migratory case, where two tasks from
> different processes play rapid ping pong. That's what I was looking at for
> various reasons.
> There the cached asid really helps by avoiding the loop completely, but
> yes, the search needs to be done for the bouncing between CPUs case.
> So maybe a combo of those might be interesting.
I'm not too worried about optimizing away the loop. It's a loop over
four or six things that are all in cachelines that we need anyway. I
suspect that we'll never be able to see it in any microbenchmark, let
alone real application.