RE: RE: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500

From: åç
Date: Mon Jul 03 2017 - 04:13:53 EST

Hi, Andreas

Actually the owl_v7_invalidate_l1 is not needed, and the headsmp-owl.S file can be removed if pen release staff is not used. The CPUx can jump to secondary_startup directly by setting OWL_CPUx_ADDR register.

Because S900 is aarch64 architecture, it cannot boot CPUx simply by setting SPS register. It depends on the low-level arm-trusted-firmware. Linux kernel can boot up CPUx by PSCI interface, and the arm-trusted-firmware will power on CPUx, initialize EL3 register and jump to EL2 entry in Linux kernel.

Best Regards,
David Liu

-----Original Message-----
From: Andreas FÃrber [mailto:afaerber@xxxxxxx]
Sent: Sunday, July 02, 2017 3:57 AM
To: åç
Cc: Arnd Bergmann; Thomas Liau; Linux ARM; mp-cs; åäé; ååç; 96boards@xxxxxxxxxxxxxx; support@xxxxxxxxxxx; Linux Kernel Mailing List; Russell King
Subject: Re: çå: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500

Hi David,

Am 01.07.2017 um 06:42 schrieb åç:
> OWL_CPUx_ADDR is the physical address of CPUx wakeup function.
> OWL_CPUx_FLAG is a valid flag of OWL_CPUx_ADDR.
> After CPUxs are wakeuped by SEV instruction, they will check their own OWL_CPUx_FLAG register. If the register vlaue is 0x55aa, CPUx will jump to OWL_CPUx_ADDR to boot up, otherwize go to sleep by WFE.
> So the pen release staff is not necessary, you can remove these code safely.

Thank you for the quick confirmation!

I have just tested a patch, and it appears to work.

Is owl_v7_invalidate_l1 necessary? mach-sunxi (that Arnd pointed to as
example) uses secondary_startup directly, without custom assembler code.

> BTW: CPU2/3 must exit the power gate state before wakeup, and CPU1 is always power on and has no power gate control.

Yes, the S500 SPS was luckily documented in the manual. The power-gating
for CPU2/3 is already implemented:

For S900 however SPS is sadly not documented... If you know who at
Actions Semi could help there, please also take a look at:

Best regards,


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