RISC-V Linux Port v4

From: Palmer Dabbelt
Date: Tue Jul 04 2017 - 15:51:50 EST

Thanks to everyone who has participated in the review process so far. There
have only been a few changes since the v3 patch set:

* The cmpxchg64 syscall is no longer enabled on 32-bit systems. It's not
possible to provide this on SMP systems, and it's not necessary as glibc
knows not to call it.

* We provide a ELF_HWCAP so users can determine the ISA of the machine the
kernel is running on.

* The multi-line comments are in a better form.

* There were a handful of headers that could be replaced with the asm-generic
versions, and a few unnecessary definitions.

* We no longer use printk, but instead use pr_*.

* A few Kconfig and defconfig entries have been cleaned up.

Since things have really calmed down, I think it would be good to try and get
this into 4.13 (ie, during this merge window). This might let us get into the
upcoming glibc release as well. Does that seem possible?

Like last time, in case one gets eaten by the mailing list this is also
available as a git tree on our Git Hub


This patch set just contains the arch code, we have various drivers that are
required to build and boot a RISC-V system. A tree that contains this patch
set merged with all our other patch sets lives at


a83d4bb70b76 pci: Add a generic, weakly-linked pcibios_fixup_bus
a3445d3b4ff1 pci: Add a generic, weakly-linked pcibios_align_resource
d97ac4f5bb1d Merge branch 'riscv-for-submission-arch-v4' into riscv-for-submission-v4
0705a31372d4 Merge branch 'riscv-for-submission-clk-v2' into riscv-for-submission-v4
a6c8eb9af199 Merge branch 'riscv-for-submission-irq-v2' into riscv-for-submission-v4
3e5b46967f66 Merge branch 'riscv-for-submission-lib-v2' into riscv-for-submission-v4
8ca3c2cdefed Merge branch 'riscv-for-submission-pci-v3' into riscv-for-submission-v4
e1aa9abddfa8 Merge branch 'riscv-for-submission-tty-v2' into riscv-for-submission-v4

If you're going to try to build or boot the kernel, I'd recommend using that.

Thanks to everyone who has helped review our port!

[PATCH 1/9] RISC-V: Init and Halt Code
[PATCH 2/9] RISC-V: Atomic and Locking Code
[PATCH 3/9] RISC-V: Generic library routines and assembly
[PATCH 4/9] RISC-V: ELF and module implementation
[PATCH 5/9] RISC-V: Task implementation
[PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI
[PATCH 7/9] RISC-V: Paging and MMU
[PATCH 8/9] RISC-V: User-facing API
[PATCH 9/9] RISC-V: Build Infastructure