Re: [PATCH] brcmnand: Fix up the flash cache register offset for older controllers

From: Brian Norris
Date: Wed Jul 05 2017 - 14:18:59 EST

Ha, I was in the middle of writing essentially this :)

On Wed, Jul 05, 2017 at 11:15:01AM -0700, Florian Fainelli wrote:
> On 07/05/2017 10:46 AM, Karl Beldan wrote:
> > From: Karl Beldan <karl.beldan-ext@xxxxxxxxxxxx>
> >
> > Tested on BCM{63138,6838,63268} and cross checked with the various
> > *_map_part.h which the brcmnand_regs_v* in brcmnand.c have historically
> > been derived from.
> BCM63138 is using a 7.0 controller, 6838 uses a 5.0 controller, but has
> a separate flash cache register which does indeed end up at 0x400 bytes
> off the main FLASH block, and finally 63268 does have a v4.0 controller
> and the flash cache is also in a separate register that makes it end up
> at 0x400.

The joy of arbitrarily-changing IP, since of course business units
within a company (or even divisions within the same business unit) would
never want to share software...

> Your change, as proposed would break chips like 7425 which use 5.0
> controller with the flash cache at 0x200 bytes.
> The binding describes an optional flash-cache register cell that you can
> specify, so that's probably what you want to do here?

What he said ^^^

The "nand-cache" register range sounds like what you're looking for.