On 07/30, Abhishek Sahu wrote:
On 2017-07-29 00:04, Stephen Boyd wrote:
>On 07/27, Abhishek Sahu wrote:
2. Following patch fixes different issue although flag name
Shall I include this patch in my patch series but not
sure we can directly turn off the PLL inside the PLL
set rate operation since it will turn the PLL off for
all its users.
Hopefully the users of a PLL that doesn't support dynamic rate
update can accept the fact that the clk will turn off while the
rate is reprogrammed. At least that seems to be true for Taniya
in that patch set. If it isn't true for your hardware, then don't
specify the flag? Or is the problem that you may not have the
flag set for certain PLLs that you're supporting?