Re: [PATCH v2] Documentation: rewrite confusing statement about memory barriers
From: Guilherme G. Piccoli
Date: Thu Sep 21 2017 - 15:53:58 EST
On 09/21/2017 04:50 PM, Paul E. McKenney wrote:
> On Thu, Sep 21, 2017 at 04:29:01PM -0300, Guilherme G. Piccoli wrote:
>> In this specific portion of the write memory barriers description,
>> the documentation mentions sequential order of stores, which is
>> confusing since sequential ordering is not guaranteed.
>> This patch tries to improve the doc in order to avoid any
>> Cc: Paul E. McKenney <paulmck@xxxxxxxxxxxxxxxxxx>
>> Signed-off-by: Guilherme G. Piccoli <gpiccoli@xxxxxxxxxxxxxxxxxx>
> Good catch, and you are quite correct, a write barrier orders only
> before and after itself, doing nothing to impose order on preceding
> writes among themselves.
That's nice, thanks a lot Paul! :)
> Applied, thank you!
> Thanx, Paul
>> v2: added Paul in CC.
>> Documentation/memory-barriers.txt | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>> diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
>> index b759a60624fd..a4bbbd1b63a0 100644
>> --- a/Documentation/memory-barriers.txt
>> +++ b/Documentation/memory-barriers.txt
>> @@ -383,8 +383,8 @@ Memory barriers come in four basic varieties:
>> to have any effect on loads.
>> A CPU can be viewed as committing a sequence of store operations to the
>> - memory system as time progresses. All stores before a write barrier will
>> - occur in the sequence _before_ all the stores after the write barrier.
>> + memory system as time progresses. All stores _before_ a write barrier
>> + will occur _before_ all the stores after the write barrier.
>> [!] Note that write barriers should normally be paired with read or data
>> dependency barriers; see the "SMP barrier pairing" subsection.